Timing-Driven Simulated Annealing for FPGA Placement in Neural Network Realization

نویسندگان

چکیده

The simulated annealing algorithm is an extensively utilized heuristic method for heterogeneous FPGA placement. As the application of neural network models on FPGAs proliferates, new challenges emerge traditional in terms timing. These stem from large circuit sizes and high heterogeneity block proportions typical networks. To address these challenges, this study introduces a timing-driven placement algorithm. This integrates cluster criticality identification during selection phase, which enhances probability high-criticality selection. In movement proposed employs improved weighted center clusters random strategy other clusters. Experimental evidence demonstrates that decreases average wire length by 1.52% critical path delay 5.03%. improvement performance achieved with marginal increase 5.01% runtime, as compared to VTR8.0.

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ژورنال

عنوان ژورنال: Electronics

سال: 2023

ISSN: ['2079-9292']

DOI: https://doi.org/10.3390/electronics12173562